ECE 3056: Architecture, Concurrency, and Energy in Computation

ECE 3056: Architecture, Concurrency, and Energy in Computation

Prerequisites: ECE 2035, ECE 2031

Course Objective:This course introduces the basic organizational principles of the major components of a processor – the core, memory hierarchy, and the I/O subsystem. Students gain an understanding of the sources of performance and energy dissipation in modern processors and learn the multiple forms and levels of parallelism that have been employed to sustain performance improvements in the industry. Assignments using architecture‐level simulators enable the students to explore the operation and tradeoffs in performance and energy and reinforce the concepts learned in the class room.

Patterson and Hennessey, Computer Organization & Design: The Hardware/Software Interface (5th edition), Morgan Kaufmann, 2014, ISBN 978-0-12-407726-3 .
Publisher Website: Supplemental Material

Course Syllabus Syllabus
Study Guide: Course Study Guide

For information about a specific semester, please refer to the class page for that semester provided by the instructor.


Module Lecture Reading (Note Appendices are found on the CD) Notes/Additional References Examples and Practice Problems
1 OverviewReview, and Introduction Ch. 1.1-1.4, 1.7-1.8  Example Review 2020-DP-Review
2  ISA: ISA & Encodings (ppt, pdf) Ch. 2.1, Figure 2.1, 2.2 – 2.7, 2.9, Figure 2.15. 2.10,2.16, 2.17  Appendix A9, A10

Class Resources Page

Some Encoding Examples (pdf)

Handy Wikipedia Ref

Example Code Segments: Arithmetic, Logical, Data. Constants

Sample Problems & Solutions

3  ISA Part II: Procedures and Program Assembly  (ppt, pdf) Ch. 2.8, 2.12 and Appendix A.1-A.6 Example Code Segments: Procedure Call

Arithmetic  Logic Unit (ppt, pdf)

Energy of Computation – Basics (ppt, pdf)

Ch. 3.2 -3.5, 3.6-3.8, and Appendix B.5 Example Code Segments: Floating Point Mean (DP, SP)

Single Cycle Datapath (pptx, pdf)

Multicycle Datapath (ppt, pdf)

Single Cycle: Section 4.1-4.4, Appendices B.7, B.8, B.11, D.2
Multi-Cycle: Appendices A.7, D.3, D.4, D.5
 Tutorial Slides on VHDL can be found here

Sample Problems & Solutions

MIPS ISA Simulation: Code and Documentation

Single Cycle Datapath: Code & Documentation

Multi Cycle Datapath: Code & Documentation

6 Performance (ppt, pdf) Ch. 1.6 For Sample Problems see Modules 5 & 7
7 Pipelined Datapath (ppt, pdf)  Sections 4.5 – 4.9

Sample Problems & Solutions

Pipelined Datapath: Code and Documentation


Caches and the Memory Hierarchy (ppt, pdf)


Section 5.2, 5.3, 5.9 Sample Problems &

Virtual Memory (ppt, pdf)


Section 5-1-5.4, 5.6, 5.8, 5.9
10 Parallelism (ILP, TLP , DLP) (ppt, pdf) Sections 6.1-6.5, 6.7 Some Additional SSE Examples:SSE1, SSE2.
Handy Wikipedia Ref for SSE
SSE Tutorial
11  Graphics Processing Units (GPUS) (ppt, pdf)  Section 6.6
12  Power Management (pptx, pdf)
13 I/O (ppt, pdf) Useful links for PCI Express, HyperTransport, Quickpath